1. Field
Embodiments of the present invention relate to a semiconductor device such as an IC, a MOS, an IGBT (insulated gate bipolar transistor), and the like, in particular to a bidirectional device or a reverse blocking IGBT, which has bidirectional blocking capability. The embodiments of the present invention also relate to a method of manufacturing such a semiconductor device.
2. Description of the Related Art
The following description is made on a reverse blocking IGBT, a type of semiconductor device. Conventional IGBTs in principal application fields of inverter circuits and chopper circuits are sufficient when provided with a forward withstand voltage. Despite existence of a reverse blocking junction, the conventional IGBTs have been fabricated with the edge of the reverse blocking junction surface exposing to the chip cutting side surface without consideration for holding reliability. In recent years, however, studies are being made on directly linked conversion circuits, for example, a matrix converter, including an AC (alternating current)/AC conversion circuit, a current source type DC (direct current)/AC conversion circuit, and some type of DC/AC conversion circuit such as a new three level circuit employing switching elements having reverse blocking capability, in order to attain reduced size and weight, high efficiency, quick response, and cost reduction.
In order to hold reverse blocking capability of a reverse blocking IGBT, a semiconductor substrate (also referred to as a wafer) after completion of manufacturing processes is cut into a multiple of semiconductor chips with a square shape and the reverse blocking pn junction in each semiconductor chip is extending bent towards the front surface side of the chip in order to avoid exposure to the cut surface in the cutting process. The edge of the pn junction is protected with an insulation film on the front surface to hold reliability. In order for the reverse blocking pn junction to extend to the front surface side, the semiconductor chip needs to comprise a diffusion layer having the same conductivity type, for example p type, as the p type collector layer in the rear surface side of the chip and connecting to the p type collector layer at one end of the p type diffusion layer and extending to the front surface at the other end. This diffusion layer is formed along the side surface of the chip. This diffusion layer formed along the side surface of the chip is referred to as an isolation layer in this specification.
FIGS. 2(a), 2(b), and 2(c) are sectional views of an essential part of a semiconductor substrate showing, in the sequence of processing steps, a method of forming an isolation layer in a conventional reverse blocking IGBT. In the method of the figures, the isolation layer is formed by means of application and diffusion. First, an oxide film 2 for a dopant mask is formed on the wafer 1 in a film thickness of about 2.5 μm by means of a thermal oxidation method as shown in FIG. 2(a). Then, in this oxide film 2, an opening 3 for diffusion of boron which is a p type impurity source is formed by patterning with a photolithography technique and etching as shown in FIG. 2(b). Then, the boron source 5 is applied at the opening 3 followed by heat treatment at a high temperature for a long time in a diffusion furnace to form a p type diffusion layer having a depth of several hundred μm as shown in FIG. 2(c). This p type diffusion layer becomes an isolation layer 4. After that, a front surface side MOS gate structure 10 is formed as shown in FIG. 3, which illustrates a completed reverse blocking IGBT. Then, the wafer is ground from the rear surface side down to the tip of the isolation layer 4 to reduce the thickness of the wafer to the depth indicated by the dotted line in FIG. 2(c). On this ground surface, a rear surface structure composed of a p type collector layer 6 and a collector electrode 7 is formed as shown in FIG. 3. Cutting the wafer along a scribe line at the position of center line in the front surface pattern of the isolation layer 4, a reverse blocking IGBT chip is fabricated as shown by the sectional view including the cut edge 8 in FIG. 3.
FIGS. 4(a), 4(b), and 4(c) are sectional views of an essential part of a wafer of a conventional reverse blocking IGBT showing another manufacturing method for forming an isolation layer in the sequence of processing steps. FIGS. 4(a), 4(b), and 4(c) are sectional views of an essential part of a semiconductor substrate showing the steps, in the sequence of processing steps, in which a trench 11 is dug vertically from the front surface of the wafer 1 and a diffusion layer is formed along the vertical side surface to obtain an isolation layer 4a that works similarly to the isolation layer 4 described previously.
First, a thick oxide film 2 with a thickness of several μm is formed as an etching mask for forming a trench as shown in FIG. 4(a). Then, a deep trench 11 with a depth of several hundred μm is formed by a dry etching technique as shown in FIG. 4(b). Subsequently, an impurity of boron is introduced to the side surface of the trench 11 by vapor phase diffusion to form a p type isolation layer 4a as shown in FIG. 4(c). The trench is filled with reinforcing material of insulation film, polysilicon or the like. Successively, processes as described previously are executed including: back grinding, formation of a front surface side MOS gate structure 10 necessary for an IGBT function, a rear surface p type collector layer 6 and a collector electrode 7. IGBT chips are cut out of the wafer 1 by dicing along scribe lines at the center of the trench 11 or at the middle of doubled trenches that are not illustrated in the figure. Thus, a reverse blocking IGBT is produced as shown in the sectional view including cut edge portion 8 in FIG. 5. This type of reverse blocking IGBT is disclosed in Patent Documents 1, 2, and 3.
In the method of forming an isolation layer of a reverse blocking IGBT by the application and diffusion process as shown in FIGS. 2(a), 2(b), and 2(c), a boron source, which is a diffusion source in a liquid state containing boron, is applied on the wafer surface followed by a thermal diffusion process. The thermal diffusion process needs a high temperature and a long time in order to form a p type isolation layer with a diffusion depth of several hundred μm. Such a thermal diffusion process causes decrease in quartz implements and jigs including a quartz boat, quartz tubes and a quartz nozzle, contamination from the heater, and loss of strength due to devitrification of the quartz implements and jigs. Increased frequency of these phenomena raises manufacturing costs. In the process of forming an isolation layer by the application and diffusion method, a thick oxide film of high quality must be used in order for the mask oxide film to endure the boron diffusion process for a long time and in order to prevent the boron from passing through the oxide film. A method of thermal oxidation is known as a method of forming a silicon oxide film of high quality to obtain a mask of high durability.
In order to exhibit effective durability of a mask oxide film even in the process of forming a p type isolation layer by boron diffusion in such conditions as a high temperature of 1,300° C., for example, and a long time of 200 hr, for example, a thermal oxidation film having a thickness of about 2.5 μm is necessary. For forming a thermal oxidation film with a thickness of 2.5 μm, a necessary oxidation time in the condition of an oxidation temperature of 1,150° C., for example, is about 200 hr for an oxidation process in a dry oxygen atmosphere that gives an oxide film of high quality. In addition, a large amount of oxygen is introduced into the wafer in those oxidation processes. The oxygen generates crystal lattice defects of oxygen precipitates and oxidation-induced stacking faults (OSF), and further produces a phenomenon of donorization of the introduced oxygen, which raises problems of deterioration of device characteristics and degradation of reliability.
The diffusion process after boron source application is usually executed in an oxygen atmosphere at a high temperature and for a long time as well, which introduces interstitial oxygen atoms within the wafer. As a result, this diffusion process also produces oxygen precipitates and donorization phenomenon of the oxygen atoms, and generates lattice defects of the oxidation-induced stacking faults (OSF) and slip dislocations. A pn junction formed in the vicinity of these lattice defects is known to cause a high leakage current and significant degradation in a breakdown voltage and deterioration of reliability of a thermally oxidized film containing such defects in the wafer. A problem also arises that oxygen atoms entered into the wafer during the diffusion process become donors causing degradation of a breakdown voltage. In the method of forming an isolation layer by application and diffusion as shown in FIG. 2, the boron diffusion isotropically proceeds in the bulk silicon towards all directions. As a result, when the boron diffusion is conducted to a depth of 200 μm, the boron diffusion simultaneously expands laterally to a range of 160 μm. This situation obstructs the object of chip size reduction.
In the method of forming an isolation layer utilizing a trench as shown in FIGS. 4(a), 4(b), and 4(c), the trench is formed by a dry etching technique and boron is introduced into the side wall of the formed trench to form a p type isolation layer. Then, the trench is filled with reinforcing material such as an insulation film, polysilicon or the like. The thus formed p type isolation layer 4a shown in FIG. 4(c), utilizing a narrow trench 11 with a high aspect ratio, is favorable for reduction in device pitch as compared with the p type isolation layer 4 shown in FIG. 2(c) formed by thermal diffusion. However, in order to carry out an etching process down to a depth of about 200 μm, a processing time of about 100 minutes is necessary for one wafer using a typical dry etching apparatus. Thus, different drawbacks arise, including an increased lead time and an increased maintenance frequency. For forming a deep trench by a dry etching process using a mask of silicon oxide (SiO2) film, a thick silicon oxide film is with a thickness of several μm since the selection ratio is not larger than 50. As a consequence, new problems arise including degradation of the rate of good products due to generation of process-induced lattice defects such as oxidation-induced stacking faults and oxygen precipitates, as well as increase in manufacturing costs. Moreover, the process for forming an isolation layer utilizing a trench with a high aspect ratio formed by the dry etching technique tends to generate a residue of chemicals 12 and residual resist material 13, which may cause a decrease in yield rate and reliability.
When a dopant such as phosphorus or boron is injected into a side wall of the trench 11, since the side wall is standing vertically, the wafer is normally tilted. The dopant injection to a side wall of a trench with a high aspect ratio has disadvantages including a decrease in effective dose amount, increased injection time, shortening of effective projection range, loss of dose amount due to screen oxide film, and deterioration of injection homogeneity. A method for injecting impurities into a trench 11 with a high aspect ratio avoiding above-mentioned problems is known, which employs vapor phase diffusion instead of ion injection. In this method, the wafer is exposed to vaporized dopant atmosphere, for example, phosphine PH3 or diborane B2H6. The vapor phase diffusion method is, however, inferior to the ion injection method with respect to controllability of the dose amount. In order to enhance strength of the wafer having a trench 11 with a high aspect ratio, a process step is necessary to fill the trench with an insulation film or polysilicon. This process step tends to leave a void in the narrow trench, which may cause a problem of deteriorated reliability.
A manufacturing method has been proposed to solve the problems discussed thus far. FIG. 17 is a partial plan view of a semiconductor substrate in relation to an etching step for forming an isolation layer in that manufacturing method. The partial plan view of FIG. 17 specifically shows nine reverse blocking IGBT chips divided by passing-through grooves in a pattern of planar lattice formed by etching on the (100) plane 23 of a wafer 1. Since the passing-through V-groove 21a is formed by wet anisotropic etching, the side surfaces of the reverse blocking IGBT are lattice planes represented by {111}. FIGS. 7(a) and 7(b) are sectional views of one chip of the reverse blocking IGBT cut out of the wafer 1 along the passing-through groove 21a indicated in FIG. 17. The double dotted curved lines in FIGS. 7(a) and 7(b) indicate existence of an omitted portion in the figures. The starting place of etching for forming the passing-through V-groove is an opposite surface of the wafer 1 in FIG. 7(a) and in FIG. 7(b). The passing-through V-groove 21a having a sectional shape of the letter V is formed on a principal surface of the wafer 1 in a planar lattice pattern by an etching process, and has a tapered surface that is the side surface 9a in FIG. 7(a) or the side surface 9b in FIG. 7(b). An isolation layer 4b is formed on the side surface region of the chip by ion injection on the side surface 9a or 9b and followed by activation annealing. The etching process for forming the passing-through V-groove fabricates tapered surfaces of four side surfaces 9a or 9b of the reverse blocking IGBT chip by means of an anisotropic etching process employing an alkali etching solution, which is disclosed in Patent Documents 4, 5, and 6.
The reverse blocking IGBT having a tapered side surface 9b as shown in FIG. 7(b) allows utilizing a wider area in the emitter side, which is the upper surface area in FIG. 7(a) and FIG. 7(b), than the IGBT having a reversely tilted side surface 9a as shown in FIG. 7(a). The IGBT of 7(b) has a wide area available for forming an n type emitter region 15 and a p type base region 16 on the emitter side surface region. Therefore, the configuration of FIG. 7(b) has an advantage that a current density is high or a chip area is reduced for the same current rating. An ion injection process for forming the isolation layer 4b in the reverse blocking IGBT shown in FIG. 7(a) and FIG. 7(b) can be carried out in a much shorter processing time than the diffusion process at a high temperature and for a long time as described previously. Consequently, the type of the IGBT as illustrated in FIGS. 7(a) and 7(b) can solve the problems altogether involved in the method of forming the isolation layer 4 by the high temperature and long time diffusion process including the problems due to lattice defects and oxygen-induced defects and the problem of damage in the diffusion furnace. As compared with the manufacturing method utilizing the vertical trench as described previously, the passing-through V-groove with a low aspect ratio has no problem of a void and a residue in the process of filing the vertical trench with an insulation film. Moreover, the IGBT with the passing-through V-groove exhibits an advantage of easy introduction of dopant by an ion injection process owing to the low aspect ratio of the V-groove.    [Patent Document 1] Japanese Unexamined Patent Application Publication No. H02-022869    [Patent Document 2] Japanese Unexamined Patent Application Publication No. 2001-185727    [Patent Document 3] Japanese Unexamined Patent Application Publication No. 2002-076017    [Patent Document 4] Japanese Unexamined Patent Application Publication No. 2006-156926    [Patent Document 5] Japanese Unexamined Patent Application Publication No. 2004-336008    [Patent Document 6] Japanese Unexamined Patent Application Publication No. 2006-303410
As disclosed in Patent Documents 4 through 6, the long time diffusion process that accompanies the disadvantages described previously can be avoided by employing the method of manufacturing a reverse blocking IGBT comprising an isolation layer formed on the tapered surface of the passing-through V-groove fabricated by an alkali anisotropic etching process. However, since the impurity distribution in the isolation layer formed by ion injection is extremely shallow, if lattice defects formed in the ion injection process are not recovered by an activation annealing process and remained in the isolation layer, the lattice defects, being located in a vicinity of a pn junction in this type of isolation layer, cause large leakage current in a reversely biased condition and a reverse blocking capability is hardly kept. Concerning a laser annealing process employed for recovery of the lattice defects, it has been found that the side surface of the isolation layer is hardly activated sufficiently and the lattice defects are not sufficiently recovered in some cases because the laser irradiation is executed in a short time of several tens of nanoseconds to several microseconds and focusing positions are different between the wafer surface and the side surface of the isolation layer. Due to narrow laser irradiation area, sufficient activation needs scanning of the narrow laser irradiation area over the whole surface of the ion injected layer. The scanning process, however, generates irradiation traces, and may adversely affect the voltage withstanding characteristics.
Another method of manufacturing a reverse blocking IGBT utilizes a tapered surface of a V-groove formed by means of alkali anisotropic etching. The V-groove in this method as shown in FIG. 8 is formed in a non-passing-through configuration with a shallow depth. A p type diffusion layer has been formed from a reversed side surface at an opposite position to the non-passing-through V-groove and exposed to the bottom surface of the V-groove. The double dotted wave-formed curves in FIG. 8 indicate existence of an omitted part in the figure. A reverse blocking IGBT can also be obtained by forming an isolation layer composed of a p type diffusion layer on the tapered surface of the V-groove of a non-passing-through type. This construction relaxes as well the problems accompanied by the diffusion process at a high temperature and for a long time. In addition, this non-passing-through type V-groove has an advantage of omitting the wafer-supporting substrate that is necessary to adhere and hold the chips cut along the passing-through V-grooves together in the reverse blocking IGBT with the passing-through V-groove as shown in FIGS. 7(a) and 7(b).
In the manufacturing process of the non-passing-through type V-grooves, however, an intersecting part is generated where the corner A with a sharp edge meets the bottom surface B of the non-passing-through type V-groove, the bottom surface B being the surface of the thin emitter side silicon, with a certain angle as shown in the perspective view of FIG. 15 illustrating one of the four corners of crossing grooves of the planar lattice pattern in the second principal surface side, that is, the rear surface side. FIG. 16(b) is a sectional view of a reverse blocking IGBT having a recessed part of the groove at the corner. The chip is mounted on a packaging substrate 20 joined with a solder 21 having the recessed edge in the rear surface side positioning in the vertically lower side. Thermal hysteresis subjected to the chip 30b in the soldering process generates thermal stress at the recessed edge part of the chip 30b due to the difference in the thermal expansion coefficients of the two different materials of the reverse blocking IGBT chip 30b and the solder 21. This thermal stress is concentrated around the intersecting parts of A and B. It has been clarified that the strain due to this stress concentration creates a crack at the edge of the chip 30b resulting in degradation of semiconductor characteristics. Even if a crack is not generated in the chip 30b, the passivation film covering the uppermost surface of the chip 30b may be peeled off, resulting in degradation of reliability. FIG. 16(a) is a sectional view of an ordinary IGBT 30a in a state joined on a packaging substrate 20 with a solder 21. This figure is shown for comparison with the construction of FIG. 16(b).